This invention relates to a method of fabricating an insulated gate type field-effect transistor (IG-FET) having excellent element characteristics and high reliability.
Heretofore, there have been attempts to reduce the size of integrated circuit (IC) devices based on scaling rules in order to improve the characteristics and to increase the integration density of the devices. For example, a high performance MOS device can be obtained by reducing the size of various parts, increasing the impurity concentration of the channel region and reducing the supply voltage.
In actual practice, however, a high performance and high integration density IC device cannot be realized by merely proportionally reducing the size of an electrode and interconnection layer, and depth of a doped region and thickness of an insulating film between different interconnection layers. Along with the proportional size reduction, the patterning precision and alignment precision of many circuit elements have to be improved. For example, 64- and 256-kbit MOS dynamic random access memories (MOS-dRAM) require patterning precision and alignment precision of approximately 0.2 .mu.m for a minimum pattern size of 2 to 3 .mu.m. Where the minimun size is 1 .mu.m or below, the necessary precision values are 0.1 .mu.m or below.
To cope with these problems, recently, there is a trend of employing dry etching in lieu of wet etching as techniques for improving the patterning precision. Particularly, a precision of 0.1 .mu.m now can be attained using reactive-ion-etching (RIE) which is a directional dry etching process. Meanwhile, the alignment precision depends on the precision of the alignment machines, so that it is difficult to secure precision below 0.1 .mu.m.
If sufficient alignment prevision cannot be obtained when fabricating a MOS device by utilizing fine processing techniques, the following problems will arise.
Firstly, the contact resistance between the source, drain regions and interconnection layers in contact therewith is increased. This is so because the contact area of the interconnection layer is made very small if a contact hole, which is essentially small in a sectional area, deviates from the source or drain region even slightly and overlays over the field region. If such a resistance increase occurs, it will lead to deterioration of the MOS device. Secondly, if a contact hole is deviated and gets out of the source or drain region even slightly due to an alignment error, a possible overetching at the time of the contact hole formation will reduce the thickness of the field insulating film adjacent to the source or drain region. As a result, it is liable that the interconnection layer of aluminum or the like penetrates the pn junction of the source or drain region, thus resulting in a junction defect. This will extremely reduce the reliability of the MOS device.